Welcome to Arm’s Neoverse. This is not The Matrix, but it is a new era for Arm in datacenters.
Arm has stepped up its game with regards to data center and communications processing. In the past, the company developed generalized intellectual property (IP) that could be used for microcontrollers, smart phones, network processors, and embedded processors. The higher performing cores eventually found its way into data centers. But as Arms ambitions for the data center and networking communications have expanded, the company needed to build more specialized cores that better address the needs of those market segments.
Previously, Arm’s architectural licensees, such as Ampere Computing (Applied Micro), Broadcom, Marvell (Cavium), Qualcomm, and others, built their own custom Arm CPU cores to meet the specific needs of networking and data center processing. But there was a demand for Arm itself to supply higher-performance CPU cores and related IP that could be licensed to a wider range of companies that didn’t have access to high-performance CPU architects. And specifically, there’s a growing interest by hyperscale cloud vendors to build their own chips. These companies may not have the capability to design CPU cores, but can build (or outsource) custom system-on-chip (SoC) that integrate licensed IP into chips. With its Neoverse product line, Arm can address this segment directly with its IP. This move toward vertical integration can be seen with Amazon’s new EC2 A1 Instance, which uses a custom AWS-built Graviton processor using Arm CPU cores. We expect more hyper-scale cloud providers will join AWS in building custom chips.
As part of its new Neoverse offerings, Arm has announced two CPU cores and a new network-on-chip (NOC) architecture that can connect 10’s of CPU cores on one die. Those cores are: the Neoverse N1 CPU for high- performance processing and the Neoverse E1 for high-throughput processing. The N1 core is targeted toward server-class processors with improved virtualization support, state-of-the-art RAS for reliable operation, security, and power and performance management capabilities. The N1 is most closely comparable to an Intel Skylake CPU generation of Intel Xeon processors. The E1 CPU core is designed for high throughput and is the first mainstream Arm core to offer multiple threads. In the past, Arm had eschewed threading as an architectural choice. Threading is the ability to run multiple instruction streams simultaneously through a single CPU core. For throughput computing, like network and communications processing, threads allow for additional simultaneous parallel processing on a set of CPU cores, which is why many of the other RISC architectures like MIPS, PowerPC, and SPARC have leveraged threading. Additionally, Both the N1 and the E1 are optimize for the latest 7 nm process nodes from TSMC and Samsung.
Tying all these high-performance cores together is Arm’s new 2D mesh network-on-chip (NOC), which efficiently connects from 8 to 128, or more, cores on one die. The limits of how many cores will fit on a single die is dependent on the process node and target die size. While these mesh interconnects are not new (we’ve seen designs going back to research at MIT back in the late 1990’s), it’s becoming preferred with large arrays of CPUs and with improved operating systems, capable of handling nonuniform memory architectures (NUMA) where cores have different latencies to main memory depending on their position in the 2D array.
As part of Neoverse, the two different types of CPU cores, the E1 and the N1, can be used together with the NOC for the construction of heterogeneous computing chips for specialized applications such as network processing. In a heterogeneous system the N1 would likely be the control plane processor responsible for managing network policies, while multiple E1 CPUs would be responsible for the data plane processing that directly processes and forwards data packets. While the E1 and N1 can share the same mesh network and memory architecture allowing for a fully coherent design, the mesh network can also be partitioned to keep control and data tasks from interfering with each other. Heterogeneous processing is becoming more important as the data processing requirements at the edge of networks are increasing. This is especially true for 5G networks that will have to handle much higher data throughput than 4G/LTE networks, yet are still power constrained by the remote locations of cellular towers.
Arm also announced a roadmap for the Neoverse N1 processors, with the introduction of a new core every year to 2021, demonstrating a significant investment and commitment to constant performance improvements. The roadmap includes the Zeus core for delivery in 2020, and the Poseidon core in 2021. In addition, the company is taking a platform approach to building an ecosystem of Arm IP along with complementary third-party IP to make reference designs that ease the job of building these custom chips. Arm and its ecosystem partners are also developing standards and a ServerReady compliance program to make software portability across multiple manufacturers.
Arm’s initial foray into servers and networking was met with slow, but steady progress, but now it looks more promising with Neoverse. Arm’s new Neoverse platform will enable higher performing and less expensive cloud and edge computing and offer cloud providers and network carriers the flexibility to build their own optimized chips and break Intel’s stranglehold on cloud data centers.
Kevin Krewell
Principal Analyst, TIRIAS Research
Twitter: @Krewell
The author and members of the TIRIAS Research staff do not hold equity positions in any of the companies mentioned. TIRIAS Research tracks and consults for companies throughout the electronics ecosystem from semiconductors to systems and sensors to the cloud.
